The present invention relates generally to semiconductor technology and more particularly to an integrated circuit interconnect.
In the manufacture of integrated circuits, after the individual devices such as the transistors have been fabricated in and on the semiconductor substrate, they must be connected together to perform the desired circuit functions. This interconnection process is generally called xe2x80x9cmetallizationxe2x80x9d and is performed using a number of different photolithographic, deposition, and removal techniques.
In one interconnection process, which is called a xe2x80x9cdual damascenexe2x80x9d technique, two interconnect channels of conductor materials are separated by interlayer dielectric layers in vertically separated planes perpendicular to each other and interconnected by a vertical connection, or xe2x80x9cviaxe2x80x9d, at their closest point. The dual damascene technique is performed over the individual devices which are in a device dielectric layer with the gate and source/drain contacts extending up through the device dielectric layer to contact one or more channels in a first channel dielectric layer.
The first channel formation of the dual damascene process starts with the deposition of a thin first channel stop layer. The first channel stop layer is an etch stop layer which is subject to a photolithographic processing step which involves deposition, patterning, exposure, and development of a photoresist, and an anisotropic etching step through the patterned photoresist to provide openings to the device contacts. The photoresist is then stripped. A first channel dielectric layer is formed on the first channel stop layer. Where the first channel dielectric layer is of an oxide material, such as silicon oxide (SiO2), the first channel stop layer is a nitride, such as silicon nitride (SiN), so the two layers can be selectively etched.
The first channel dielectric layer is then subject to further photolithographic process and etching steps to form first channel openings in the pattern of the first channels. The photoresist is then stripped.
An optional thin adhesion layer is deposited on the first channel dielectric layer and lines the first channel openings to ensure good adhesion of subsequently deposited material to the first channel dielectric layer. Adhesion layers for copper (Cu) conductor materials are composed of compounds such as tantalum nitride (TaN), titanium nitride (TiN), or tungsten nitride (WN).
These nitride compounds have good adhesion to the dielectric materials and provide good barrier resistance to the diffusion of copper from the copper conductor materials to the dielectric material. High barrier resistance is necessary with conductor materials such as copper to prevent diffusion of subsequently deposited copper into the dielectric layer, which can cause short circuits in the integrated circuit.
However, these nitride compounds also have relatively poor adhesion to copper and relatively high electrical resistance.
Because of the drawbacks, pure refractory metals such as tantalum (Ta), titanium (Ti), or tungsten (W) are deposited on the adhesion layer to line the adhesion layer in the first channel openings. The refractory metals are good barrier materials, have lower electrical resistance than their nitrides, and have good adhesion to copper.
In some cases, the barrier material has sufficient adhesion to the dielectric material that the adhesion layer is not required, and in other cases, the adhesion and barrier material become integral. The adhesion and barrier layers are often collectively referred to as a xe2x80x9cbarrierxe2x80x9d layer herein.
For conductor materials such as copper, which are deposited by electroplating, a seed layer is deposited on the barrier layer and lines the barrier layer in the first channel openings to act as an electrode for the electroplating process. Processes such as electroless, physical vapor, and chemical vapor deposition are used to deposit the seed layer.
A first conductor material is deposited on the seed layer and fills the first channel opening. The first conductor material and the seed layer generally become integral, and are often collectively referred to as the conductor core when discussing the main current-carrying portion of the channels.
A chemical-mechanical polishing (CMP) process is then used to remove the first conductor material, the seed layer, and the barrier layer above the first channel dielectric layer to form the first channels. An abrasiveless chemical is used for the chemical-mechanical polishing process in order to prevent abrasives from being left in the channel. When a layer is placed over the first channels as a final layer, it is called a xe2x80x9ccappingxe2x80x9d layer and a xe2x80x9csinglexe2x80x9d damascene process is completed. When the layer is processed further for placement of additional channels over it, the layer is a via stop layer.
The via formation step of the dual damascene process starts with the deposition of a thin via stop layer over the first channels and the first channel dielectric layer. The via stop layer is an etch stop layer which is subject to photolithographic processing and anisotropic etching steps to provide openings to the first channels. The photoresist is then stripped.
A via dielectric layer is formed on the via stop layer. Again, where the via dielectric layer is of an oxide material, such as silicon oxide, the via stop layer is a nitride, such as silicon nitride, so the two layers can be selectively etched. The via dielectric layer is then subject to further photolithographic process and etching steps to form the pattern of the vias. The photoresist is then stripped.
A second channel dielectric layer is formed on the via dielectric layer. Again, where the second channel dielectric layer is of an oxide material, such as silicon oxide, the via stop layer is a nitride, such as silicon nitride, so the two layers can be selectively etched. The second channel dielectric layer is then subject to further photolithographic process and etching steps to simultaneously form second channel and via openings in the pattern of the second channels and the vias. The photoresist is then stripped.
An optional thin adhesion layer is deposited on the second channel dielectric layer and lines the second channel and the via openings.
A barrier layer is then deposited on the adhesion layer and lines the adhesion layer in the second channel openings and the vias.
Again, for conductor materials such as copper and copper alloys, a seed layer is deposited by electroless deposition on the barrier layer and lines the barrier layer in the second channel openings and the vias.
A second conductor material is deposited on the seed layer and fills the second channel openings and the vias.
A CMP process is then used to remove the second conductor material, the seed layer, and the barrier layer above the second channel dielectric layer to form the first channels. When a layer is placed over the second channels as a final layer, it is called a xe2x80x9ccappingxe2x80x9d layer and the xe2x80x9cdualxe2x80x9d damascene process is completed.
The layer may be processed further for placement of additional levels of channels and vias over it. Individual and multiple levels of single and dual damascene structures can be formed for single and multiple levels of channels and vias, which are collectively referred to as xe2x80x9cinterconnectsxe2x80x9d.
The use of the single and dual damascene techniques eliminates metal etch and dielectric gap fill steps typically used in the metallization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum (Al) to other metallization materials, such as copper, which are very difficult to etch.
A major problem with using copper in the conductor core is that copper tends to migrate into the dielectric layer in a process known as diffusion. The migration of copper atoms can lead to electrical short circuits, rendering the circuit unusable. Barrier layers deposited by self-ionized plasma (SIP) deposition have traditionally had high barrier resistance to limit the diffusion of copper atoms, but as the dimensions of semiconductor devices shrink in the quest to improve chip performance, the proportional scaling of barrier layer dimensions in vias leads to extremely thin (10-20 angstroms) via sidewalls.
In addition, the size reductions have caused the channels to be closer together which requires the use of low dielectric constant (low-k) dielectric materials having dielectric constants under 3.9. These dielectric materials are porous and, where the barrier depositions were formerly conformal to the conventional dielectric constant dielectric materials, the barrier layers are no longer conformal to these materials. In addition, these depositions have been found to damage the dielectric materials as well as causing poor adhesion to seed layers.
Both the thinness of the barrier layer, and its now non-conformal characteristic, has led to its ineffectiveness as a diffusion barrier and also to the formation of voids in the associated seed layer and conductor core leading to reductions in electromigration (EM) resistance.
Diffusion relates to the movement of copper atoms from the conductor core into the dielectric layer, causing short circuits and EM relates to the movement of copper atoms under influence of current, particularly at the interface between layers or areas of poor adhesion, which form voids that can lead to an open circuit in the via.
While the problems have been well known and many attempts have been made to solve individual problems, a solution that would solve all the problems has long been sought by those skilled in the art.
The present invention provides a manufacturing method, and an integrated circuit resulting therefrom has a substrate and a semiconductor device thereon. A stop layer over the substrate has a dielectric layer formed thereon having an opening into which a conformal barrier is formed. A conformal barrier liner is formed in the opening, processed, and treated to improve adhesion. Portions of the conformal barrier liner on the sidewalls act as a barrier to diffusion of conductor core material to the dielectric layer. A conductor material in the opening over the vertical portions of the conformal barrier liner and the stop layer complete the conductor core. The integrated circuit has reduced size and good barrier resistance to electro-migration.